A prior art method of forming a contact plug to a gate, source or drain region of a MOS device is provided in connection with FIGS. 1-1B. A MOS device structure is shown in FIG. 1. Methods for fabricating the structure of FIG. 1 are well known in the art of integrated circuit fabrication, as described in, for example, U.S. Pat. No. 6,232,224 to Inoue and U.S. Pat. No. 6,350,636 to Lee et al., the entirety of which are hereby incorporated by reference herein. The MOS device of FIG. 1 is fabricated on a substrate 2, such as a silicon substrate, and is isolated from other devices by shallow trench isolation (STI) 4. A gate dielectric 6, such as an oxide, is formed on the substrate 2 along with gate electrode 8, often formed from polysilicon. The device also includes lightly doped regions 10 and more heavily doped source/drain regions 12. Spacers 14, usually of silicon oxide, and metal silicide layers 16 are also provided. A layer of silicon nitride 18, which serves as an etch stop layer as described below, is disposed over the MOS device, along with an interlayer dielectric or insulating layer 20.
Referring to FIG. 1A, a photoresist layer 22 is patterned and formed over the interlayer dielectric film 20 to expose a small area of the film 20 over gate 8 or source/drain 12. An etch process is then executed to open contact tunnel 24 through interlayer dielectric film 22 down to the etch stop layer 18 above the selected contact region. This etch stop layer helps protect side wall spacers 14 from being etched. After the contact tunnel 24 is formed, a second etch step is performed to remove the etch stop layer 18 to expose the desired metal silicide contact region 16. A wet etch process is also performed to remove the photoresist 22 and any polymer remaining from the aforementioned etch steps. As shown in FIG. 1B, a contact plug 26 is then deposited to form a contact to the exposed metal silicide region 16. An additional cleaning step may also be performed to smooth the silicide region and remove any native oxide before depositing the contact plug 26.
Metal silicide layers 16 are usually either cobalt, tungsten, or titanium silicides. Tungsten silicide layers are typically used for 0.35 μm processes, titanium silicide is used for 0.25 μm processes, and cobalt silicide is usually selected for 0.13-0.18 μm processes. Nickel silicide contacts have been proposed for newer processes, such as 0.13 μm and smaller processes, in order to provide resistivity reductions and to take advantage of nickel silicide's low leakage or diffusion characteristics. A problem arises, however, when opening contact holes to nickel silicide contact regions using prior art processes. These processes typically use CF based etchants, such as CHxFy/O2 and CxFy/O2 and it is believed that the O2, F and/or CO components of either or both of the photoresist removal etchant or the etch stop layer removal etchants react with the nickel silicide contact regions, resulting in contact resistivity (Rc) failure—essentially an open circuit. This is generally not a concern when cobalt silicide contact regions are utilized, as described in Inoue, because cobalt silicide is more stable than nickel silicide and does not suffer from the consequent contact Rc failure issue.
Therefore, there is a need for a new method of forming contacts to a device. To that end, there remains a need for a new method of opening contact tunnels to silicide contact regions, such as nickel silicide contact regions, when forming contact plugs to an integrated circuit device.